In a digital system, a reference clock may be used to synchronize communications between components. The reference clock signal may be generated by a clock generator, which may be a standalone component in the digital system. FIG. 1 illustrates a clock driver circuit design in a memory subsystem. The memory subsystem includes a memory controller 102, a plurality of dynamic random access memories (DRAMs) 104, a clock generator 110 which utilizes a reference resistor Rref 112, and a clock line 106 which is connected to a termination voltage Vt 114 through a termination resistor Rt (or more generally a resistive termination network 108). In the example memory subsystem shown in FIG. 1, the clock line 106 includes a conductor that passes through the memory controller 102 such that the conductor is divided into two portions: a clock-to-master (CTM) portion and a clock-from-master (CFM) portion. The memory controller 102 is the master device in the system. The CTM portion propagates the clock signal from the clock generator 110 towards the memory controller 102. The CFM portion propagates the clock signal from the memory controller 102 towards the DRAMs 104. The DRAMs 104 are connected to both CTM and CFM portions of the clock line. The clock line 106 is divided in this manner so that the clock signal can maintain a specific phase relationship with data signals (not shown) that are transmitted between the DRAMs 104 and the memory controller 102 as the signals propagate, regardless of whether the data signals are transmitted from the DRAMs to the memory controller or vice versa.
FIG. 2 is a waveform illustrating the clock signal generated by the clock generator 110 (also called a clock driver circuit) of FIG. 1 as a function of time. The example clock signal has a high voltage level V0h, a low voltage level V0l, and a midpoint centered around Vref. The clock signal is converted into an internal clock signal for use within the DRAMs by circuitry (not shown) within the DRAMs. The circuitry generates the internal clock signal by comparing the voltage of the clock signal with the reference voltage Vref.
In typical clock generators, the reference resistor Rref 112 determines the amplitude of the output signal. As the clock signal is used by all components of the system as a precise timing reference, the precision of the Rref is critical in a memory subsystem design. Therefore, the Rref usually resides outside the clock generator because it is more cost effective to achieve a precise resistance value using a standalone resistor as opposed to implementing the Rref resistor on chip.
From a system perspective, the optimal amount of voltage swing depends on the number of DRAM devices on the reference clock network, since each DRAM device is a load to the reference clock signal. For example, a clock generator supplying the reference clock for a 32-device memory channel should preferably drive a larger output swing to overcome signal attenuation in the channel than it would need to for a memory channel that has only 16 devices loading the reference clock lines. The larger voltage swing in the long channel improves the voltage margin at the expense of the increased power.
One of the problems of the clock driver circuit illustrated in FIG. 1 is that the voltage swing of the clock generator is fixed for a given configuration of DRAM devices in the memory subsystem. That is, the precision reference resistor Rref is tuned to operate with a certain memory configuration at a certain clock frequency. This reference resistor is fixed on the circuit board after it is tuned to operate with the memory topography at a particular clock frequency. However, if it is desired to change the memory topography of an existing memory subsystem, the existing clock signal would not produce an optimal voltage swing for the new memory subsystem. For example, if more DRAM devices are added to the memory configuration, the load on the output of the clock generator 110 would increase. Hence, the clock signal quality received at the DRAM devices would suffer because of the attenuation caused by the additional loads. On the other hand, if a number of DRAM devices are removed from the memory configuration, the load of the clock circuit would decrease. Hence, the clock generator would drive a larger voltage swing to the clock signal line due to the reduction in the number of loads. This increase in voltage swing unnecessarily consumes more power.
In view of the shortcomings of the systems described above, it is an objective of the present invention to provide a clock driver circuit that adjusts its drive strength in response to a change in clock frequency of the memory subsystem. It is another objective of the present invention to provide a clock driver circuit that adjusts its drive strength in response to a change in memory configuration of the memory subsystem. More generally, it is an objective of the present invention to provide a clock driver circuit that generates a signal on a clock line with these characteristics.